A 4-ns 4K 1-bit two-port BiCMOS SRAM
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چکیده
T’fris paper introduces a two-port BiCMOS static memory cell that combines ECL-level word-linevoltageswingsandemitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access (CSEA) cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAM’S while preserving the high density and low power of CMOS memory arrays. The memory cau be read and written simrdtaueously and is therefore well-suited to applications such as high-speed caches and video memories. A READaccesstime of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K X I-bit two-port memory integrated in a 1.5pm 5-GHZ BiCMOS technology. The access time in tfris prototype design is nearly temperature insensitive, increasing to only 4 ns at a case temperature of 100”C.
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